Sunday , January 17 2021

Intel introduced a new architecture for 2019: Sunny Cove

Okay, not everything is so sunny, but it's a nice picture of a cove.

Okay, not everything is so sunny, but it's a nice picture of a cove.

In 2019, Intel will release Core and Xeon chips built around a new architecture: the chips will add a bunch of new instructions to speed up some popular workloads such as cryptography and compression, with the company displaying 75% of generation.

Starting in 2015, Intel's core processors, Core and Xeon, are based around Skylake's architecture. Intel's original intention was to let Skylake into the 14-meter production process and then follow it with Cannon Lake for its 10-meter process. Cannon Lake will add several new features (for example, if there are more AVX instructions), but otherwise it will be exactly the same as Skylake.

However, delaying the 10nm process effectively forced Intel to stick to 14nm for longer than expected. Accordingly, the company follows Skylake (with up to four cores in consumer systems) with Kaby Lake (with higher clock frequencies and much higher hardware acceleration of modern video codecs), Lake Lake (up to eight cores) and Whiskey Lake improved integrated chipset) . Skylake's main architecture was not changed in these variants, which means that while their clock frequencies are different, the number of cycle instructions (IPC) is essentially identical.

Looking at the sunny side of 10nm

Intel says that Sunny Cove, by contrast, is an enhanced microarchitecture that will be built on the 10-meter process of the company. While still retrieving from Skylake, it has been improved to perform more instructions in parallel and with lower latency, and some buffers and caches have also been expanded. The level 1 data cache is 50% higher than Skylake, as well as the cache for decoded microprojects and cache level 2 (with the exact size depending on market positioning). When Skylake has two reservation stations that send instructions on the eight ports with up to four instructions sent per cycle, Sunny Cove has four reservation stations, ten ports and up to five instructions per cycle. Execution elements are also slightly reorganized, with the Sunny Cove having an extra unit capable of handling LEA instructions (a very universal x86 instruction that can perform different arithmetic operations as well as calculate memory addresses) and the other for vector shuffling . This should give the extra machine more opportunities for how to plan instructions and therefore to get more parallelism.

Where Skylake can carry two loads and one warehouse per cycle, Sunny Cove deals with loads and two stores. The reload buffer is larger, allowing extraordinary instructions during flight, and the loading and stowage buffers are also larger, allowing for more in-flight operations.

Like the comprehensive Cannon Lake processor, built at 10nm and available in limited quantities, Sunny Cove includes support for the AVX-512 instructions. The AVX-512 covers many different extensions and capabilities; some are general-purpose arithmetic, others are specialized for loads like neural networks. Like those, Sunny Cove will include new instructions for speeding up encryption and data compression load – these are the new instructions that are responsible for 75 percent performance improvement.

Five-byte RAM

Sunny Cove made the first major change in support for x64 virtual memory, as AMD introduced an x86-64 64-bit x86 expansion in 2003. Although the virtual memory addresses used for these systems accept 64 bits of storage, they actually contain only 48 useful bits of information. Bits from 0 to 47 are used with the top 16 bits, from 48 to 63, all copies of bit 47. This limits the virtual address space to 256TB. These virtual addresses are mapped to physical addresses using a four-level page table structure, with physical memory addresses also limited to 48 bits. This means that these systems can support a maximum of 256TB of physical memory.

Both Intel and AMD have shared these boundaries since 2003. No longer: Sunny Cove expands virtual addresses to 57 meaningful bits (with top 7 bits again or all zeros or all, copying bit 56) with physical memory addresses up to 52 bits. To do this, a fifth step in the page table is required. New restrictions allow 128PB of virtual address space and 4PB physical memory.

Different iterations of Skylake gave us better clock speeds and higher core calculations. But what they have not done is to improve the IPC of the single-threaded code. For the first time since 2015, it will make Sunny Cove everyone workload faster, and not just those that can spread in an increasing number of threads.

Intel promises a Core Cove CPU with the Core brand in the second half of 2019. In 2020 it will be followed by Willow Cove, Sunny Cove with revised cache, new security features and new transistor optimization. In 2021, the company will release Golden Cove, again with more security features, but also promises improved single thread productivity, better machine learning performance and better networking and 5G performance.

Sunny Cove comes to Xeon. The road map here is less clear – Intel does not offer dates – but we will see Cascade Lake in the early part of 2019, bringing new instructions for AVX-512 for neural networks and up to 48 cores. This will be followed by Cooper Lake, which will include data support bfloat16 – a formatted floating point format that is used in neural networks. This will be followed by Sunny Cove in the Xeon Mask: Ice Lake. From there, a next-generation processor will follow.

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